Semiconductor non-volatile memories, comprising an array of non-volatile memory cells arranged in a plurality of rows and columns (or bit lines) can be characterized as operating either in a NAND mode of operation or a NOR mode of operation. The reference to NAND or NOR type refers to the manner in which the non-volatile memory cells are arranged in the array and are programmed and read. Typically, NAND memory cells are programmed or read to operate in a page mode manner in which a page of data (typically 512 bytes) is stored in a plurality of latches (or plurality of page buffers) that are integrated with the memory circuit device. During programming, a page of data is externally supplied to the NAND device and is stored in the page buffer. From the page buffer, the data is then stored in the NAND cells. Reading of the integrated memory circuit device causes data from a page of the memory cells to be read and stored in a page of latches. Thereafter, the contents of the page of latches are read, typically in a serial manner from the integrated memory circuit device.
In contrast, in a NOR mode of operation, different bytes within the NOR array can be randomly accessed, read or programmed. The difference in operation between these two types of modes of operation is that typically, a NOR operation for random access read or program of a small amount of data is faster compared to a NAND program or read operation. However, for a page of serial data, NAND operation of program or read, which requires 2–7 usec of overhead, is faster (on a per byte basis) than compared to a NOR mode of operation.
A NOR memory device emulating the operation of a NAND device is disclosed in U.S. Pat. No. 6,469,955, whose disclosure is incorporated by reference in its entirety.